Paper 2005/146

A High Speed Architecture for Galois/Counter Mode of Operation (GCM)

Bo Yang, Sambit Mishra, and Ramesh Karri

Abstract

In this paper we present a fully pipelined high speed hardware architecture for Galois/Counter Mode of Operation (GCM) by analyzing the data dependencies in the GCM algorithm at the architecture level. We show that GCM encryption circuit and GCM authentication circuit have similar critical path delays resulting in an efficient pipeline structure. The proposed GCM architecture yields a throughput of 34 Gbps running at 271 MHz using a 0.18 um CMOS standard cell library.

Metadata
Available format(s)
PDF
Publication info
Published elsewhere. Unknown where it was published
Keywords
Authenticated Encryption ModeGCM
Contact author(s)
smishr01 @ utopia poly edu
History
2005-06-03: last of 4 revisions
2005-05-19: received
See all versions
Short URL
https://ia.cr/2005/146
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2005/146,
      author = {Bo Yang and Sambit Mishra and Ramesh Karri},
      title = {A High Speed Architecture for Galois/Counter Mode of Operation (GCM)},
      howpublished = {Cryptology ePrint Archive, Paper 2005/146},
      year = {2005},
      note = {\url{https://eprint.iacr.org/2005/146}},
      url = {https://eprint.iacr.org/2005/146}
}
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