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Paper: The SPEEDY Family of Block Ciphers: Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures

Authors:
Gregor Leander , Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany
Thorben Moos , Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany
Amir Moradi , Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany
Shahram Rasoolzadeh , Radboud University, Nijmegen, The Netherlands
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DOI: 10.46586/tches.v2021.i4.510-545
URL: https://tches.iacr.org/index.php/TCHES/article/view/9074
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Abstract: We introduce SPEEDY, a family of ultra low-latency block ciphers. We mix engineering expertise into each step of the cipher’s design process in order to create a secure encryption primitive with an extremely low latency in CMOS hardware. The centerpiece of our constructions is a high-speed 6-bit substitution box whose coordinate functions are realized as two-level NAND trees. In contrast to other low-latency block ciphers such as PRINCE, PRINCEv2, MANTIS and QARMA, we neither constrain ourselves by demanding decryption at low overhead, nor by requiring a super low area or energy. This freedom together with our gate- and transistor-level considerations allows us to create an ultra low-latency cipher which outperforms all known solutions in single-cycle encryption speed. Our main result, SPEEDY-6-192, is a 6-round 192-bit block and 192-bit key cipher which can be executed faster in hardware than any other known encryption primitive (including Gimli in Even-Mansour scheme and the Orthros pseudorandom function) and offers 128-bit security. One round more, i.e., SPEEDY-7-192, provides full 192-bit security. SPEEDY primarily targets hardware security solutions embedded in high-end CPUs, where area and energy restrictions are secondary while high performance is the number one priority.
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BibTeX
@article{tches-2021-31325,
  title={The SPEEDY Family of Block Ciphers: Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universität Bochum},
  volume={2021, Issue 4},
  pages={510-545},
  url={https://tches.iacr.org/index.php/TCHES/article/view/9074},
  doi={10.46586/tches.v2021.i4.510-545},
  author={Gregor Leander and Thorben Moos and Amir Moradi and Shahram Rasoolzadeh},
  year=2021
}