Paper 2014/013

A Novel Modular Adder for One Thousand Bits and More Using Fast Carry Chains of Modern FPGAs

Marcin Rogawski, Kris Gaj, and Ekawat Homsirikamol

Abstract

In this paper a novel, low latency family of adders and modular adders has been proposed. This family efficiently combines the ideas of high-radix carry-save addition and the parallel prefix networks. It also takes advantage of fast carry chains of modern FPGAs. The implementation results reveal that these hybrid adders have great potential for efficient implementation of modular addition of long integers used in various public key cryptography schemes.