Paper 2011/176

A FPGA pairing implementation using the Residue Number System

Sylvain Duquesne and Nicolas Guillermin

Abstract

Recently, a lot of progresses have been made in software implementations of pairings at the 128-bit security level in large characteristic. In this work, we obtain analogous progresses for hardware implementations. For this, we use the RNS representation of numbers which is especially well suited for pairing computation in a hardware context. A FPGA implementation is proposed, based on an adaptation of Guillermin's architecture which computes a pairing in 1.07 ms. It is 2 times faster than all previous hardware implementations (including ASIC and small characteristic implementations) and almost as fast as best software implementations.

Metadata
Available format(s)
PDF
Category
Public-key cryptography
Publication info
Published elsewhere. Unknown where it was published
Contact author(s)
sylvain duquesne @ univ-rennes1 fr
History
2011-04-08: received
Short URL
https://ia.cr/2011/176
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2011/176,
      author = {Sylvain Duquesne and Nicolas Guillermin},
      title = {A FPGA pairing implementation using the Residue Number System},
      howpublished = {Cryptology ePrint Archive, Paper 2011/176},
      year = {2011},
      note = {\url{https://eprint.iacr.org/2011/176}},
      url = {https://eprint.iacr.org/2011/176}
}
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