Paper 2020/1369

Multiplication over Extension Fields for Pairing-based Cryptography: an Hardware Point of View

Arthur Lavice, Nadia El Mrabet, Alexandre Berzati, and Jean-Baptiste Rigaud

Abstract

New Number Field Sieves (NFS) attacks on the discrete logarithm problem have led to increase the key size of pairing-based cryptography and more precisely pairings on most popular curves like BN. To ensure 128-bit security level, recent costs estimations recommand to switch for BLS24 curves. However, using BLS24 curves for pairing requires to have an efficient arithmetic in Fp4. In this paper, we transposed previous work on multiplication over extesnsion fields using Newton's interpolation to construct a new formula for multiplication in Fp4 and propose time x area efficient hardware implementation of this operation. This co-processor is implemented on Kintex-7 Xilinx FPGA. The efficiency of our design in terms of time x area is almost 3 times better than previous specific architecture for multiplication in Fp4. Our architecture is used to estimate the efficiency of hardware implementations of full pairings on BLS12 and BLS24 curves with a 128-bit security level. This co-processeur can be easily modified to anticipate further curve changes.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint. MINOR revision.
Contact author(s)
arthur lavice @ external thalesgroup com
History
2020-11-02: received
Short URL
https://ia.cr/2020/1369
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2020/1369,
      author = {Arthur Lavice and Nadia El Mrabet and Alexandre Berzati and Jean-Baptiste Rigaud},
      title = {Multiplication over Extension Fields for Pairing-based Cryptography: an Hardware Point of View},
      howpublished = {Cryptology ePrint Archive, Paper 2020/1369},
      year = {2020},
      note = {\url{https://eprint.iacr.org/2020/1369}},
      url = {https://eprint.iacr.org/2020/1369}
}
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