Paper 2021/309

SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous Resets

Xingyu Meng, Kshitij Raj, Atul Prasad Deb Nath, Kanad Basu, and Sandip Ray

Abstract

Modern SoC designs include several reset domains that enable asynchronous partial resets while obviating complete system boot. Unfortunately, asynchronous resets can introduce security vulnerabilities that are difficult to detect through traditional validation. In this paper, we address this problem through a new security validation framework, SoCCCAR, that accounts for asynchronous resets. The framework involves (1) efficient extraction of reset-controlled events while avoiding combinatorial explosion, and (2) concolic testing for systematic exploration of the extracted design space. Our experiments demonstrate that SoCCAR can achieve almost perfect detection accuracy and verification time of a few seconds on realistic SoC designs.

Metadata
Available format(s)
PDF
Category
Applications
Publication info
Published elsewhere. Minor revision. Design Automation Conference
Keywords
Hardware Security VerificationSoCConcolic Testing
Contact author(s)
kanad basu @ utdallas edu
History
2021-03-09: received
Short URL
https://ia.cr/2021/309
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2021/309,
      author = {Xingyu Meng and Kshitij Raj and Atul Prasad Deb Nath and Kanad Basu and Sandip Ray},
      title = {SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous Resets},
      howpublished = {Cryptology ePrint Archive, Paper 2021/309},
      year = {2021},
      note = {\url{https://eprint.iacr.org/2021/309}},
      url = {https://eprint.iacr.org/2021/309}
}
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